High-speed interface links connecting two devices over a physical cable are typically serial communication links. Examples for such links include, but are not limited to, a high-definition multimedia interface (HDMI), a digital video interface (DVI), DisplayPort (DP), Universal Serial Bus 3 (USB3), and others.
During the process of data transmission, a transmitter continuously transmits signals to a receiver. The receiver uses a clock and data recovery (CDR) circuit to generate a clock corresponding to the incoming data stream, thereby correctly retiming the incoming data. Clock and data recovery (CDR) circuits may be based on a phase-locked loop (PLL) or an over-sampler. A PLL based CDR circuit generates a clock from an approximate frequency reference and uses the generated clock to phase-align to the transitions in the data stream with the PLL. The generated clock is a recovered clock transmitted by the transmitter.
Typically, the physical cable exhibits the characteristics of a low-pass filter. Therefore, the amplitude of the recovered data, received at the receiver, is attenuated and the phase is distorted. Also, the physical cable typically consists of wires which are not perfectly shielded. Thus, noise is present in the recovered data due to cross coupling between signals from different wires.
Transmitted serial signals can be modulated using, for example, N-pulse amplitude modulation (N-PAM), where N discrete voltage levels are used to encode input bits. The two common PAM techniques utilized to modulate high-speed serial signals are 2-PAM (also known as non-return-to-zero “NRZ”) or 4-PAM. In a 2-PAM two levels are used to encode a single bit. In a 4-PAM, two bits are mapped to one of four possible differential voltage levels, for example, −3 volts, −1 volt, 1 volt, and 3 volts. Demodulation is performed by detecting the amplitude level of the carrier at every symbol period. The 4-PAM allows transmitting signals at double the rate of the 2-PAM signal, but the loss of 4-PAM modulated signals is higher than that of 2-PAM modulated signals. Experiments have shown that when the loss of the physical medium is more than 10 dB, the 4-PAM has been used in preference to 2-PAM.
When transmitting 4-PAM modulated signals, the receiver should implement a CDR circuit for recovering such signals. However, 4-PAM CDR circuits are more complex than 2-PAM CDR circuits. In addition, 2-PAM CDR circuits cannot be utilized to recover 4-PAM modulated signals. Some solutions discussed in the related art provide a 4-PAM CDR circuit that can handle 2-PAM and 4-PAM modulated signals. For example, the 2-PAM/4-PAM is discussed in IEEE publication titled “Equalization and Clock Recovery for a 2.5-10-Gb/s 2-PAM/4-PAM Backplane Transceiver Cell” to Zerbe, et al. However, Zerbe's proposed circuit is a 4-PAM CDR circuit that has been adapted to also handle 2-PAM signals.
One of the difficulties when implementing 4-PAM CDR circuits is to detect the correct point to sample the incoming data stream, as each 2-bit may include four transitions. Thus, detecting a correct sampling point may be a challenge. Existing solutions try to overcome this problem by generating control signals to control the CDR circuit, to change the location of the data to be sampled by the CDR circuits. The control signals are generated by comparing the current bit with the previous bit. However, such solutions require re-design of CDR circuits to support the new control. Thus, a 2-PAM CDR circuit cannot be utilized to recover 4-PAM or N-PAN (N>2) signals.
It would be, therefore, advantageous to provide a solution for clock and data recovery of N-PAM modulated signals using a 2-PAM CDR circuit.